As is well recognized, a problem posed by mixed sampled-data analog/digital systems is that of controlling the characteristics of the treated signal for optimization of its processing.
Errors in the width of the expected signal, as well as biasing and sampling errors, are usually estimated by means of specific monitoring circuits, which will modify the parameters of the whole processing system by specifically acting on their section dedicated to the analog pre-processing step.
A prior analog/digital processing system is shown schematically as 1 in FIG. 1. The analog/digital processing system has an input terminal IN1 receiving an input signal Sin to be treated, and an output terminal OUT1 delivering a treated output signal Sout.
The analog/digital processing system 1 includes an analog filter circuit 2 and a digital processing circuit 3, connected in series with each other between the input terminal IN1 and the output terminal OUT1.
In particular, the analog filter circuit 2 has an input terminal 12 connected to the input terminal IN1 of the analog/digital processing system, and an output terminal O1 connected to an input terminal 13 of the digital processing circuit 3, having in turn an output terminal O3 connected to the output terminal OUT1 of the analog/digital processing system 1.
The output terminal O2 of the analog filter circuit 2 is connected to a control terminal TC2 thereof, through a series of a monitoring circuit 4 and a controller 5.
More particularly, the output terminal O2 of the analog filter circuit 2 is connected to an input terminal 14 of the monitoring circuit 4, having in turn an output terminal O4 connected to an input terminal 15 of the controller 5. The controller 5 has an output terminal O5 connected to the control terminal TC2 of the analog filter circuit 2.
In general, the controller 5 is a Proportion-Integral-Derivative (PID) circuit, that is a circuit capable of producing a correcting signal S5 which is proportional to the combination of the first derivative and the integral of an error signal S4 produced by the monitoring circuit 4, and a term proportional to the error signal S4.
Since the characteristics of the signal Sin to be treated are usually known, this simple class of PID controllers is sufficiently versatile. It is indeed possible to employ different monitoring circuits for phase, offset, and gain signals from the analog/digital processing system 1, which monitoring circuits will not interact with one another, so that separate controllers can be obtained which are adapted to independently act on different parameters, specifically of the analog portion of the analog/digital processing system 1.
The monitoring circuit 4 is input a filtered signal S2, and outputs an error signal S4 which is a non-linear function of the input signal and proportional to the estimated characteristic of the treated signal Sout.
Integrating the monitoring circuit 4 and the controller 5 to the digital domain is a convenient choice. It should be noted, however, that, for systems which are operated at high frequencies, the processing of the signal Sin to be treated must be split over several clock cycles.
Thus, a latency is introduced in the control loop formed of the monitoring circuit 4 and the controller 5, which latency imposes constraints to the loop gain of the analog/digital processing system 1, thereby penalizing its overall performance.
Latency means here a predetermined delay in the transmission of data through the control loop, that is a delay between the application of a stimulus, or perturbation, to the control loop input and the first correction thereof being output from the control loop, which delay is usually expressed as clock cycles.
It could be considered to compensate for the degraded performance of the analog/digital processing system 1 by adopting a more sophisticated design for the controller 5. But in actual practice, this would reflect in the latency of the control loop being further increased.
The need to keep latency low, felt especially in applications where the clock cycle is a very short one, leads to compromising by the use of a low-versatility controller which is granted a sufficiently long time for the system to converge on optimum parameters; this implies that, during a processing step, data will be preceded by a preamble of sufficient length to allow the monitoring-controller loop to settle.
A first prior solution to the problem of reducing the control loop latency consists of using a controller 5 which includes a PLL or phase-locking loop 6.
FIG. 2 shows schematically a linearized model of such a prior controller 5, including a phase-locking loop generally denoted by the numeral 6. Specific reference will be made, purely for illustrative purpose, to the instance of a sampling step controller 5, the considerations made herein below being of more general merit.
Specifically for processing that signal, the PLL controller 5 is to be applied to a phase detector, assumed for simplicity to be working in a linear mode, i.e., in a near-locking condition.
The PLL controller 5 has at its input an adder node .SIGMA.1 which receives a first signal in on an adder terminal (+) and a second signal VCOn on a subtract terminal (-), and delivers a regulated phase signal .PHI.n on an output terminal O1. The PLL controller 5 includes a loop filter 7, formed of a simple controller PI, and a voltage/frequency converter 8, modeled as a simple integrator, which are connected in series with each other between the output terminal O1 and the subtract terminal of the adder .PHI.1.
The PLL controller 5 exhibits a latency M, schematically represented by a latency block 9, and a loop gain vco gain, schematically represented by a gain block 10.
The loop filter 7 has first A and second B characteristic parameters, being respectively an integral gain and a proportional gain, whose variations govern the stability of the analog/digital processing system 1 whereto the PLL controller 5 is applied. In particular, as the latency M increases, the range in which the system 1 remains stable against the varying characteristic parameters A and B becomes increasingly narrower, and the choice of these integral A and proportional B gains is greatly restrained in consequence.
When a PLL controller 5 of this type is used, it becomes impossible to optimize, for example, the control time of convergence during the preamble. It matters to observe that, not even by substituting, for the PI filter 7, some general-purpose filter of greater complexity characterized by a frequency response with two poles and two zeroes, can any substantial improvement be achieved in the system characteristic.
The reason for such deep influence of the latency M on the performance of the controller 5 formed with a phase-locking loop 6 can be appreciated from an inspection of the position of the roots of the controller 5, as shown in FIG. 3.
This controller 5 has M poles at the origin due to the latency M, and has two poles at +1 and a zero at 1-A/B which are tied to the loop filter-voltage/frequency converter combination.
An analysis of the position of the roots in FIG. 3 shows that the poles which tend to exit the unity circle first are those of the position branches with origin at +1; also, such poles originate the slowest modes of the PLL controller 5, at any values of the loop gain vco gain of the phase-locking loop 6, due to they being bounded within the sector (defined by the polar coordinates (.theta., r)): ##EQU1##
Since the ratio A/B is to approach unity for the PLL controller 5 to be stable, the available range is apparently limited. It should be noted, however, that in any case, where higher values of the latency M than 5 must be accepted for design reasons, a unity increase of the latency would not alter the characteristics of the PLL controller 5 to any significant extent.
FIG. 4 shows the form of the amplitude response of the PLL controller 5. In particular, the graph of FIG. 4 is plotted to a log scale, with the value 1 placed at a frequency f=1/2T, T being the clock period of the analog/digital processing system, and relates to a PLL controller 5 with latency M=8.
In accordance with the foregoing, this pattern remains virtually unchanged throughout its right-hand half as the characteristic parameters A and B of the loop filter 7 vary.
FIG. 5 shows patterns for a band limit at -3 dB of the PLL controller 5 against the parameter A, with the normalized values of the parameter B along the abscissa axis. In particular, the band limit is marked along the ordinate axis as a percent fraction of 1/2T.
From the graphs of FIGS. 4 and 5, it can be concluded that the only portion of the frequency response of the PLL controller 5 which is affected by variations of the characteristic parameters A and B of the loop filter 7 of the phase-locking loop 6 is the low-frequency portion, since the remainder of the response is dependent on the positions of the poles introduced by the latency M; the positions of these poles are essentially defined solely by the loop gain vco gain of the phase-locking loop 6.
It should be noted that the use of a loop filter with a more complicated architecture than that shown in FIG. 2 would not enhance the controller versatility to any satisfactory extent, nor would it enhance that of the analog/digital processing system as a whole. The analog/digital processing system 1 derives its inherent limitation from relation (1) above.
In particular, a rough formula can easily be derived for the upper band limit of the analog/digital processing system 1, which is substantially unrelated to the controller architecture. Since the branches emanating from +1 are linked angularly as follows: ##EQU2## it is, ##EQU3## With 1/2T being the extreme band of the system 1 at a clock period T, it is apparent, as well as confirmed by equation (3) above, that the controller 5 can only "shape" a fraction of the useful band.
It should also be appreciated that the stability range of the controller 5 will decrease as the latency M increases in the phase-locking loop 6 because the effect of a correction can only be noticed after a time duration equal to the latency M. During this time, the system will be under the effect of the control.
As the latency M increases, for the same characteristics of the controller 5, it is obviously necessary to reduce the loop gain vco gain, since the corrective effect would dwell longer.